Scaling bulk technology beyond the 20 nm node faces formidable challenges, particularly for low power (LP) applications, partially due to the competing requirements of density, power, and performance, and partially due to increased device variation and parasitics. System-on-chip (SoC) applications require various sets of transistors to achieve optimal tradeoff between power and performance.
Furthermore, as the pitch continues to scale, being able to land contacts in the correct location becomes more and more difficult. Full metal gate technology enables implementation of self-aligned contacts. Multiple threshold voltage (Vt) is a significant technology requirement for SoC applications. Fully depleted devices such as extremely thin silicon-on-insulator (ETSOI) or FinFET (fin-type field effect transistor) typically require work function tuning to obtain different Vt, which cannot be done through channel doping.